The SP series logic analyzers are designed to perform and analyze 9 channels of logic signals and industrial buses with a frequency of 200 MHz. This is perfect for demanding applications where logic signals with maximum resolution must be captured on all channels.
The SP209 logic analyzers are based on the ScanaStudio software (Windows, Mac, Linux) to acquire, display, analyze and decode signals. Most industry standard protocols can be interpreted, including: SPI, I2C, USART, 1-wire, CAN, LIN, I2C, RS232, RS485, TWI and many more. More than 30 protocols are available.
Logic analyzers and protocol decoders of the SP209 series offer a detailed analysis of logic signals and protocols with a timing resolution of 200 MHz (5 ns). The 9-channel operation enables the acquisition of 8-bit parallel data together with a clock or strobe signal. The SP series consists of two devices, SP209 and SP209i:
|Ikalogic SP209 Logic Analyzer
||Ikalogic SP209i Logic Analyzer (Industrial Version)
Logic channels can be multiplexed with dedicated industrial inputs that can be connected directly to RS232, RS485, CAN and LIN buses.
- 9 logical channels with adjustable threshold values (1.8 V, 2.5 V, 3.3 V, 5 V)
- State-of-the-art input stage with Schmitt triggers that eliminate glitches on slow signals
- 200 MHz sampling rate, used with all 9 channels
- Option for external clock (state mode) up to 50 MHz
- Precise trigger-in and trigger-out signals on SMA ports
- Sample compression and streaming via USB.
- 2GB DDR-3 memory starts when USB is not fast enough
- Integrated receiver in industrial version: SP209i (RS232, CAN, LIN, RS485)
Embedded 2Gb Sampling memory
The built-in embedded 2Gb sampling memory always guarantees high computing power. Logic analyzers of the SP series compress and stream recorded signals via USB 2.0 to a Windows, Linux or MacOS PC. The USB bandwidth can vary from system to system and is practically limited to 20 MB / s. For this reason, SP logic analyzers have an integrated 2 Gbit DDR-3 memory, which temporarily saves the acquired samples at 1.6 GB / s and thus avoids the USB restrictions.
- Flank trigger
- Logic change on one or more channels
- Trigger on a sequence of timed logic signals
- Trigger on a protocol word or event (e.g. serial word or confirmation of the I2C address)
- ext. Trigger input
- ext. Trigger output
- multi-stage trigger system
- Two-stage trigger (e.g. first edge trigger, then trigger on I2C address)