I3C Bus

I3C (Improved Inter Integrated Circuit) is also known as MIPI I3C and SenseWire. I3C is an emerging industry standard for multidrop serial data buses. I3C was developed in 2016 in cooperation between electronics and computer-related companies and the Mobile Industry Processor Interface Alliance (MIPI Alliance).  I3C adds a significant number of system interface features while retaining upward compatibility with existing I²C slave devices while native I3C devices support higher data rates, similar to Serial Peripheral Interface (SPI). With I3C one or more master devices can be connected to one or more slaves over the bus. Prodigy Technovations is one of the first manufacturers to offer an I3C protocol analyzer for this purpose.

 

Purpose of I3C

I3C was initially intended for mobile applications as a single interface that can be used for all digitally interfaced sensors. But now it's also for all mid-speed embedded and deeply embedded applications across sensors, power regulators, actuators, MCUs, and FPGAs... I3C improves upon the features of I2C while maintaining backward compatibility. The interface is useful for other applications, as it offers high-speed data transfer at very low power levels while allowing multi-drop between the host processor and peripherals, which is highly desirable for any embedded system.

The main purpose from the mipi alliance: 

  • To standardize sensor communication,
  • To reduce the number of physical pins used in sensor system integration,
  • To support low power, high speed, and other critical features that are currently covered by I²C and SPI

 

I3C the evolution of I²C

I²C (Inter-Integrated Circuit) was developed in 1982 and is a serial synchronous two-wire bus. It is still the industry standard for monitoring, diagnostic and control solutions in many embedded applications. I2C is easy to implement, low in cost and fast in high speed mode (Hs-mode) up to 3.4 Mbps. I2C is a true bidirectional two-wire bus in a master / slave architecture with software addressing and integrated transmission protocol. It requires only one clock line SCL (Serial Clock Line) and one data line SDA (Serial Data Line).

This means that a microcontroller can control multiple chips with only two I / O pins and simple software. Originally, the I2C bus was designed for interactions between a few ICs mounted on the same board, such as controlling the tuning of TV sets or radios.

The increasing numbers of sensors in mobile devices require application processors and/or sensor hubs with a higher number of logic pins used for sensor communication and control. In a typical application, multiple digital communication interfaces are used along with supporting logic lines for dedicated interrupt and sleep signals. Top tier smartphones include 10 or more sensors and a critical point has been reached where 20 or more logic signals are required.

 

I3C-Design

Further deficits of I2C: 

  • The inability of the sensor slaves to initiate communication
  • The overhead protocol that reduces throughput 
  • The pull-up resistors limit the clock speed and increases the power dissipation 

 

I3C eliminates the fragmentation of digital Interfaces

If large amounts of data need to be transferred is an another de facto standard the SPI interface (Serial Peripheral Interface). SPI requires four communication lines:

  • Serial Clock (SCLK) is the output from the master for synchronization
  • Master Output, Slave Input, or Master Out Slave In (MOSI | SIMO)
  • Master Input Slave Output, or Master In Slave Out (MISO | SOMI)
  • SS: Slave Select (often active low, the output is from master)

Many features are not clearly defined in the SPI standard. Because of this, many settings are required and this leads to different and incompatible devices. 

With I3C there is a consistent method for communication with the different sensors. This prevents integration problems as developers are no longer confronted with the fragmentation of the digital interfaces (I2C, SPI, UART, ...).

Main features I3C: 

  • Simple like I2C, low pin count and easy board design
  • Multi-Drop (vs. point to point)
  • Higher Data Rates
  • Simpler Pads
  • Low Power of SPI
  • Higher Throughput for a given frequency
  • In-band Interrupts (from Slave to Master) 
  • Dynamic Addressing
  • Advanced Power Management
  • Hot-Join

 

I3C host adapter and I3C protocol analyzers

The PGY-I3C-EX-PD series is the global solution for testing I3C designs. The PGY-I3C-EX-PD series devices can be master or slave damage to the I3C data traffic with error injections that decode the I3C protocols.

Prodigy's I3C Analyzer and Exerciser series include a lite version and a full version with full functionality and maximum hardware performance.

 

 

 

      PGY-I3C-EX-PD (Fullversion)

 

 

I3C-EX-PD-I3C-Protocol-Exerciser-and-Analyzer
 
 

Analyzer

Check  Full range of functions

Check

 Compatible with I2C / I3C (V1.1 / 1.0) bus systems

 

Exerciser

Check

 SCL frequency: 400 KHz - 13,5 MHz

 CheckUser defined I3C / I2C traffic generation 

Check

 Compatible with I2C/ I3C (V1.1/1.0) bussystems

Check

 Configurable: 1 master + 3 slaves

 CheckGradually adjust the operating voltage

Check Simulated real-time network traffic

Check Custom communication delay

Check Supports a variety of error injections

Check

 API for Python and C ++ available

 

 

      PGY I3C-EX-PD (Lite-Version)

 

 

I3C-EX-PD-I3C-Protocol-Exerciser-and-Analyzer
 
 

Analyzer

Check Full range of functions (except adv. Trigger)

Check

 Compatible with I2C / I3C (V1.1 / 1.0) bus systems

 

Exerciser

Check

 SCL frequency: 400 KHz to 13.5 MHz

 CheckCustom I3C / I2C traffic generation

Check

 Compatible with I2C / I3C (V1.1 / 1.0) bus systems

Orang_minus

 Configurable: 1 master + 1 slave 

Orang_minus

 Fixed operating voltage (1.2V / 1.8V / 2.5V / 3.3V)

No

 No simulated real-time network traffic

No

 No custom communication delay

No

 No error injection

No

 No API support