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PGY-LA-EMBD | Cross Logic & Protocol Analyzer |
Channels |
Max 10 channels Logic Channels |
State Speed |
100MS/S (Synchronous capture) |
Number of State clock support |
Two. Flexibility to sample at rising or falling edge |
Timing Speed |
Up to 1GS/S (Asynchronous capture) |
Record Length |
Smart Continuous streaming of data to HDD/SSD of host computer |
Voltage level support |
0 to 5V, Flexibility to define logic threshold |
Waveform Plot |
Plots waveforms with flexible configurable bus diagram |
List View |
List all the data samples at each sampling point |
Trigger for LA |
Pattern Trigger, pulse width trigger, delay trigger |
Protocol Decode Support |
I2C, SPI, UART, I3C, SPMI, RFFE |
Simultaneous decoding of I2C,
SPI, UART |
Yes. Connect I2C, SPI and UART bus to Logic Analyzer.
Simultaneously captures the bus data and displays it in time
correlated view with corresponding time waveforms |
Protocol View with Timing view
(PA+Sys) |
Displays the protocol decoded data with high sample rate timing
waveform at the same time |
API Support |
Displays the protocol decoded data with high sample rate timing
waveform at the same time |
Connector type |
Flying Lead probe cable, female.#10 clip-on banana connectors as
optional accessories. |
External Triggers |
Trigger Out
SMA connector |
Markers |
SIX markers with delta information between two markers. |
Views |
Timing View
State/Logic/Waveform Listing View
Protocol View
Bus-Diagram to display Protocol packets with timing diagram plot |
Protocol Trigger |
Auto (Trigger on any packet)- Default
Pattern trigger
Protocol aware trigger-
UART: Start bit ,Parity Bit, Data
SPI : Clock, Chip Select, MOSI Data, MISO data
I2C: Start bit, Address, Data, Address plus Data, Ack, Nack,
Repeated Start, Stop bit
Timing parameter trigger: Pulse width (Positive or Negative) in ns.
Delay Trigger |
Capture duration |
Smart streaming of Protocol Data to host HDD/SSD |
Report |
Report in PDF, CSV formats |
Host Connectivity |
USB 3.0 |
Dimensions |
140mmx100mmx35mm |
Weight |
200 gms |
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