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I3C, SPI & SPMI protocol & simultaneous logic analyzer

Product no.: PGY-LA-EMBD

In Stock, Delivery within 1-2 working days

Regular price

1,200.00 €

from 999.00 €

Netto

€ incl. 19% VAT

Volume Discounts on request

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Logikkanäle

Possible delivery methods: DHL Express Delivery, DHL standard delivery | Switzerland, DHL standard delivery, DHL standard delivery, DHL standard delivery, Own carrier number

Logic Analyzer for embedded Systems

10 channels with Protocol and Logic Analysis capability.
Simultaneous Logic and Protocol Analysis of UART, SPI, I2C, I3C, RFFE & SPMI.
Protocol activity with time stamp information
Fixed problems at circuit and system level.

An innovation for the development of embedded systems

PGY-LA-EMBD is an industry first logic analyzer in its category which enables engineers to debug timing problems and perform simultaneous protocol analysis of I2C, SPI , UART, I3C, RFFE & SPMI interfaces in embedded designs. This enables designers debug circuit level and system level problems quickly.

PGY-LA-EMBD offers 1GS/Sec asynchronous (timing) data and 100Mhz synchronous (state) data capture which makes it an ideal debug tool to address the digital design problems. Designers can now easily analyze setup and hold time issues, glitches and synchronous data activities apart from analyzing protocol issues.
Current generation embedded designers need to collect data from multiple interfaces such as I2C, SPI, UART, I3C, RFFE & SPMI and process it to achieve optimal performance of their designs.

Embedded design teams need to take timely action to meet the intended objectives of the product. PGY-LA-EMBD simultaneously decodes I2C, SPI, UART, I3C, RFFE & SPMI bus and displays the protocol activitywith time stamp information. PGY-LA-EMBD is an ideal instrument to debug the hardware and embedded software integration issues and optimize the software performance. Multiple markers enable smart delta measurements which are key to designers. Zoom enables users to look at specific areas of the signal.

Solving Embedded Hardware Issues

10 Channels logic analyser with timing and state analysis capability.
100 MHz Synchronous state analysis helps idenify embedded design signal behavior.
Asynchronous timing analysis helps identify glitches.
Debugging timing issues in hardware with 1GS/s per channel timing acquisition.
Delay and Pulse width trigger feature to capture elusive hardware design issues.

Solving Embedded Software Issues

Simultaneous multi protocol support: UART, SPI, I2C, I3C, RFFE & SPMI.
System level insights to protocol messages.
Multiple markers to resolve protocol messages timing issues.

Features of the PGY-LA-EMBD Cross Logic & Protocol Analyzer

10 channels with Protocol and Logic Analysis capability.
1GS/Sec Timing (Asynchronous) Analysis
100MHz State (Synchronous) Analysis
Simultaneous Protocol Analysis of UART, SPI, I2C I3C, RFFE & SPMI.
Detailed Trigger capabilities: Auto, Pattern, Protocol aware (UART, SPI, I2C, I3C, RFFE & SPMI) and timing (pulse width and delay).
Smart streaming of data from Protocol. Analyzer to host computer for long duration capture using USB3 interface.
Innovative easy to use Graphical user interface.
Error Analysis of Protocol packet
Provides timing, waveform, listing and Protocol listing views
Detailed filtering capability for protocol decoded data
PDF and CSV report format.
API support.

FREE Technical Support

Via Email and phone

FREE Software Upgrades

for unlimited time

REQUEST Demo Unit

Test the device for free

With Every Purchase of a Device, you will receive

Documentation and Manual to debug and develop your System

Free technical support via E-Mail and Phone.

Free minor upgrades and bug fixes as they become available.

Interfaces in Embedded Designs

A typical embedded design mainly has various integrated circuits interconnected using different interfaces based on the architecture needs, The typical interfaces that we come across in any embedded designs are the legacy RS-232, RS-422 and UART and the currently used interfaces like SPI and I2C which are likely to be replaced by the newer I3C. It is good to understand these interfaces, their advantages and limitations to help designers choose the right interface for their specific eco system design needs.

Electronics Circuit

Multiple interfaces like UART/SPI/I2C are used in inter chip communications. The I2C comm-unication protocol uses only two bidirectional open collector or open drain lines, Serial Data Line (SDA) and Serial Clock Line (SCL), pulled up with resistors. Traditionally typical voltages used have been +5 V or +3.3 V; however, recently +2.5 V, +1.8 V, and +1.2 V have become more common.

Industrial Automation

RS-232/RS-422/UART/SPI/I2C are relevant interfaces used in m/c to m/c communication.
The universal asynchronous receiver trans-mitter (UART) takes bytes of data and trans-mits the individual bits in a sequential fashion. At the reciever, a second UART re-assembles the bits into complete bytes. Each UART contains a shift register, which is the funda-mental method of conversion between serial and parallel forms.

Motor Controls

Three signals are shared by all devices on the SPI bus: SCLK, MOSI and MISO. SCLK is gen-erated by the master device and is used for
synchronization. MOSI and MISO are the data lines. The direction of transfer is indicated by their names. Data is always transferred in both directions in SPI, but an SPI device inter-ested in only transmitting data can choose to ignore the receive bytes.

Medical Electronics

RS-232/SPI/I2C are common interfaces used in medical electronics.

I2C is well suited for boards with many de-vices connected on the bus. This helps re-duce the cost and complexity of the circuit as additional devices are added to the system

Lightning Controls

SPI is a very simple communication protocol. It does not have a specific high-level protocol which means that there is almost no over-head. Data can be shifted at very high rates in full duplex. This makes it very easy to use and efficient in a single master single slave condition. With no limitation on the data rate SPI becomes the choice where data rates are important

Defense and Education

RS-232 is a standard originally introduced in 60s for serial communication transmission of data. It defined signals connecting between a DTE (data terminal equipment) such as a computer terminal, and a DCE (data circuit-terminating equipment or data communication equipment), such as a modem. The standard
defines the electrical characteristics and tim-ing signals, the details of the signals, and connectors details.

Due to the large number of different interfaces in an embedded system, the PGY-EMBD Cross Logic & Protocol Analyzer is the ideal tool for developing or debugging an embedded design. You can find detailed information about the functions of the device under the Features tab.

Feature Overview of the PGY-LA-EMBD Cross Logic & Protocol Analyzer

Comprehensive data and system monitoring is possible using the PC monitoring software. The PGY-LA-EMBD Cross Logic & Protocol Analyzer grants the embedded design engineer unprecedented access to the developing embedded overall system. The Embedded System Analyzer is ready for use within seconds, an example setup is shown in the graphic below.

Easy Configuration

Users can easily configure the Logic Analyzer for embedded interfaces by either selecting Logic Analysis(LA) mode or Protocol Analysis (PA) mode or a combined (LA+PA) mode. This ensures a quick and easy way to configure the product and look at complex problems at system level either in Logic Analysis (State Analysis, Timing Analysis) or Protocol decoding or both. Save and Recall capability ensures designers can recall their custom setup details.

Multiple Views

Multiple domain Views provide the necessary complete view of all supported interfaces’ state, timing and protocol activity. Users can easily setup the analyzer to view timing, logic and protocol decode views to enable easy insights to the design. User can set different trigger conditions from the setup menu to capture timing and protocol activity at specific events. The decoded results can be viewed in timing, logic and protocol listing window with auto correlation. This comprehensive view of information makes it industry’s best, offering an easy to use solution to debug the embedded interfaces protocol activity and analyze timing issues. Multiple cursors help designers to look into details of their design performance.

Timing View

Timing view is a unique capability of the PGY-LA-EMBD which enables designers to get detailed insights to their signals timing information. The timing view uses internal clock signal to plot the waveform. The flexible sampling rate selection enables designers to investigate Glitches which can cause issues in the functioning of their designs. Grouping feature enables designers to group various related signals for better viewing and analysis. Marker and Zoom features make it convenient to analyze any timing errors. Ability to analyze any point in the captured data record ensures easy debug and analysis over a long capture duration.

State View/Waveform Listing View

State view helps designers to see the actual signal behavior. Using the device clock as reference, it provides the plot of clock and data signals with bus diagram. Grouping of signals ensures designers have the flexibility to view signals together. All signals are time correlated to help look into setup and hold times, pulse width, missing data etc. which are very critical for digital designs as designers look to optimize their codes.

Protocol Decode View

Protocol Activity window provides the decoded packet information in each state and all packet details with error info in the packets. This gives the system level insight to the design teams. The individual protocol decodes windows based on selected interfaces ensures easy viewability for design teams. Selected frame in Protocol listing window will be auto correlated in timing view to view the timing information of the packet. Protocol errors will be highlighted to ensure designers are alerted to the same easily.

Powerful Trigger Capabilities

PGY-LA-EMBD supports Auto, pattern, Protocol aware and timing parameter trigger capabilities. Users can trigger on any of the Protocol packets. Comprehensive Trigger provides the flexibility to monitor different conditions.

Analytics

Detailed analytics on various protocol to enable better analysis and provide additional insights to designers.

Report

Report can be generated in PDF or CSV format with details of all the signal information, plots and custom details like name of the company, logo, tester name, date and time to ensure designers can document all details and share the report.

	PGY-LA-EMBD \| Cross Logic & Protocol Analyzer
Channels	Max 10 channels Logic Channels
State Speed	100MS/S (Synchronous capture)
Number of State clock support	Two. Flexibility to sample at rising or falling edge
Timing Speed	Up to 1GS/S (Asynchronous capture)
Record Length	Smart Continuous streaming of data to HDD/SSD of host computer
Voltage level support	0 to 5V, Flexibility to define logic threshold
Waveform Plot	Plots waveforms with flexible configurable bus diagram
List View	List all the data samples at each sampling point
Trigger for LA	Pattern Trigger, pulse width trigger, delay trigger
Protocol Decode Support	I2C, SPI, UART, I3C, SPMI, RFFE
Simultaneous decoding of I2C, SPI, UART	Yes. Connect I2C, SPI and UART bus to Logic Analyzer. Simultaneously captures the bus data and displays it in time correlated view with corresponding time waveforms
Protocol View with Timing view (PA+Sys)	Displays the protocol decoded data with high sample rate timing waveform at the same time
API Support	Displays the protocol decoded data with high sample rate timing waveform at the same time
Connector type	Flying Lead probe cable, female.#10 clip-on banana connectors as optional accessories.
External Triggers	Trigger Out SMA connector
Markers	SIX markers with delta information between two markers.
Views	Timing View State/Logic/Waveform Listing View Protocol View Bus-Diagram to display Protocol packets with timing diagram plot
Protocol Trigger	Auto (Trigger on any packet)- Default Pattern trigger Protocol aware trigger- UART: Start bit ,Parity Bit, Data SPI : Clock, Chip Select, MOSI Data, MISO data I2C: Start bit, Address, Data, Address plus Data, Ack, Nack, Repeated Start, Stop bit Timing parameter trigger: Pulse width (Positive or Negative) in ns. Delay Trigger
Capture duration	Smart streaming of Protocol Data to host HDD/SSD
Report	Report in PDF, CSV formats
Host Connectivity	USB 3.0
Dimensions	140mmx100mmx35mm
Weight	200 gms
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Available Documents

In the following you will find the data sheet, the brochure and the one page flyer of the PGY-LA-EMBD Cross Logic & Protocol Analyzer.

Datasheet

PGY-LA-EMBD Datasheet

Version 1.0

One Page Flyer

PGY-LA-EMBD One Page Flyer

Version 1.0

Brochure

Embedded Interface Brochure

Version 1.0

Delivery Content

Included Parts	Optional Parts
1x PGY-LA-EMBD (v 1.0): Logic Analyzer for Embedded Interfaces	PGY-LA-EMBD-Cable: Flying lead probe cable with female connector to connect to DUT
1x USB3.0 cable	PGY-LA-EMBD banana clips ( set of #10)
1x PGY-LA-EMBD Software (Donwload and CD)
1x Flying lead probe cable with female connector to connect to DUT

Customer ratings for I3C, SPI & SPMI protocol & simultaneous logic analyzer

Number of ratings: 1
Average rating: 5

Das Gerät ist Spitze.
from Anonymous on 03/02/2021

Das Gerät ist Spitze. Die simultane Logik- und Protokollanalyse ermöglicht es, Fehler wesentlich schneller zu identifizieren.

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Plus Vat for enduser and companies located in Germany

Browse these categories as well: Logic Analyzer, I²C, SPI, UART / RS232, Embedded Logic Analyzer

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Homepage Products Logic Analyzer I3C, SPI & SPMI protocol & simultaneous logic analyzer

I3C, SPI & SPMI protocol & simultaneous logic analyzer

Logic Analyzer for embedded Systems

An innovation for the development of embedded systems

Solving Embedded Hardware Issues

Solving Embedded Software Issues

Features of the PGY-LA-EMBD Cross Logic & Protocol Analyzer

Interfaces in Embedded Designs

Electronics Circuit

Industrial Automation

Motor Controls

Lightning Controls

Defense and Education

Datasheet

One Page Flyer

Brochure

Customer ratings for I3C, SPI & SPMI protocol & simultaneous logic analyzer

We also recommend

Good Reasons for eVision

Payment methods

My Account

Legal Terms

Our best price gurantee