An innovation for the development of embedded systems
PGY-LA-EMBD is an industry first logic analyzer in its category which enables engineers to debug timing problems and perform simultaneous protocol analysis of I2C, SPI , UART, I3C, RFFE & SPMI interfaces in embedded designs. This enables designers debug circuit level and system level problems quickly.
PGY-LA-EMBD offers 1GS/Sec asynchronous (timing) data and 100Mhz synchronous (state) data capture which makes it an ideal debug tool to address the digital design problems. Designers can now easily analyze setup and hold time issues, glitches and synchronous data activities apart from analyzing protocol issues.
Current generation embedded designers need to collect data from multiple interfaces such as I2C, SPI, UART, I3C, RFFE & SPMI and process it to achieve optimal performance of their designs.
Embedded design teams need to take timely action to meet the intended objectives of the product. PGY-LA-EMBD simultaneously decodes I2C, SPI, UART, I3C, RFFE & SPMI bus and displays the protocol activitywith time stamp information. PGY-LA-EMBD is an ideal instrument to debug the hardware and embedded software integration issues and optimize the software performance. Multiple markers enable smart delta measurements which are key to designers. Zoom enables users to look at specific areas of the signal.