PGY-UART-EX-PD UART Exerciser & Analyzer

Product no.: PGY-UART-EX-PD
Available delivery methods: DHL Express Delivery, DHL standard delivery | Switzerland, DHL standard delivery, DHL standard delivery, DHL standard delivery, Own carrier number

UART Exerciser & Protocol Analyzer

The UART Protocol Analyzer (PGY-UART-EX-PD) is a feature-rich protocol analyzer for capturing and debugging communications between the host and the design under test. PGY-UART-EX-PD is the leading tool that design and test engineers can use to test the respective UART designs for their specifications by configuring the PGY-UART-EX-PD as a master/slave, generating UART traffic and decoding the UART protocol decoding packets




Key Features

  • Supports custom UART traffic generation
  • Simultaneous UART traffic generation and protocol decoding on the bus
  • Variable UART baud rates
  • Continuous streaming of protocol data to the host computer to provide a large buffer
  • Timing diagram of the protocol-decoded bus
  • List view of protocol activity
  • Error analysis of protocol decoding
  • Ability to write a training script to combine the generation of multiple data frames at different data rates
  • USB 2.0/3.0 interface to the host computer
  • API support for automation in Python or C++







Multi Domain View

The multi-domain view provides a complete view of UART protocol activity in a single GUI. The user can easily set up the analyzer to generate UART traffic via a GUI or script. The user can capture the protocol activity on a specific event and decode the transition on the UART line. The decoded results can be displayed in the timing diagram and the protocol listing window with autocorrelation. 








Exerciser Function


PGY-UART-EX-PD supports the generation of UART traffic via GUI and script. The user can use the GUI to generate simple traffic to test the DUT. The scripted GUI provides the flexibility to emulate all real world traffic including error injections. 










View of the time diagram and log listing

The timing view provides a display of the transmit signals with bus diagram. The overlay of the log bits on the digital timing waveform facilitates debugging of the decoded log data. The cursor and zoom functions make it easier to analyze the protocol in the timing diagram for any timing errors. Protocol window provides the decoded packet information in each state and all packet details with error info in packet. Selected frame in Protocol listing window will be auto correlated in timing view to view the timing information of the packet.





Setup View


The user can configure the PGY-UART-EX-PD for different baud rates, data widths and stop bits. The user can also choose whether the parity is odd or even, depending on the data type used, and also select the data type.






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